Capacitive lead-frame sensing technologies are typically used to detect opens between an integrated circuit (IC) signal pin and a mounting substrate (e.g., a printed circuit board). The amplitude of the alternating current (AC) stimulus is normally set to a level that ensures that semiconductor junctions, from which the functional circuitry of the integrated circuit is formed, do not turn on. The primary concern with turning on semiconductor junctions is damage to the IC device being tested due to excessive current.
When semiconductor junctions are turned on, the current supplied from the stimulus must be limited in magnitude and duration to prevent damage. The traditional semiconductor junction turns on at an AC stimulus of approximately 700 mV peak. Thus, the typical AC test stimulus for capacitive lead-frame technologies has been set around 200 mV, at which it is assumed that the junction current is insignificant to device damage and measurement stability.
Semiconductor junctions in newer technologies do not necessarily turn on at the traditional 700 mV due to advancements in semiconductor processing technology (shrinking geometries, changes in doping materials and doping concentrations, etc.) Furthermore, the knee at which these newer semiconductor junctions turn on is not necessarily a sharp transition at a single threshold voltage, but instead is a curve that could transit a significant voltage range. It is also common for a single IC to contain multiple groups of pins that have different junction characteristics.
Almost all pins on modern ICs include some level of protection for electrostatic discharge (ESD). ESD protection circuits commonly incorporate one or more diodes (semiconductor junctions) designed to turn on and discharge energy before any damage is done to internal circuitry. A simple example of traditional ESD protection circuitry is shown in FIG. 1 for an example circuit device, shown at 1, that includes at least one input 2 and one output 8. As shown, the input 2 receives a signal INPUT to be driven to internal circuitry 5. ESD protection on the input 2 includes a first pair of diodes 3, 4 (one 3 forward biased from ground to the input node 2, and the other 4 forward biased from the input node 2 to the power source VCC), which protects the internal circuitry 5 connected to the input 2. ESD protection on the output 8 includes a second pair of diodes 6, 7 (one 6 forward biased from ground to the output 8, and the other 7 forward biased between from the output 8 to the power source VCC), which protects the internal circuitry 5 connected to the output 8.
When one refers to a diode “turning on”, one is usually referring to the voltage level (typically referred to as the “threshold voltage”) at which the forward conducting current becomes significant. In reality, diodes conduct some current even before the knee at which the current becomes exponentially greater. FIG. 2 shows the traditional diode curve that might be exhibited by the circuit in FIG. 1. Assuming that only one diode is forward conducting at once and that the other conducts a minuscule reverse current, the circuit in FIG. 1 reduces to a simple diode and can be understood using the simplified diode equation:
                    i        =                              I            0                    ⁡                      (                                          e                                  qV                  nkT                                            -              1                        )                                              Equation        ⁢                                  ⁢                  (          1          )                    
where i is the diode current in amps, Io is the reverse saturation current in amps, q is the electron charge in coulombs, V is the diode voltage in volts, n is a dimensionless ideality factor, k is Boltzmann's constant, and T is the temperature in Kelvins.
As shown in FIG. 2, the circuit 1 in FIG. 1 has a recognizable forward conducting knee (shown at 15) of 700 mV at which the current is approximately 0.5 nA. The current at 200 mV (500 mV below the knee) is a mere 50 fA and unlikely to affect the capacitive lead-frame measurements.
The current-voltage (IV) curve of FIG. 2 is not necessarily representative of all semiconductor junctions in newer technologies. Moreover, not all newer technologies will use a simple protection circuit as shown in FIG. 1 because changing input/output (IO) standards may require protection of even lower voltage logic due to higher energy levels.
An alternative circuit shown in FIG. 3 employs a two-stage approach to ESD protection of sensitive circuits. The behavior of the circuit in FIG. 3 cannot be modeled by Equation 1. Even though ESD protection circuits for newer technologies are not predictable, however, at the basic level they almost invariably consist of one or more semiconductor junctions that either explicitly or implicitly carry some of the same characteristics as a diode. One characteristic is a non-linear current-voltage (IV) curve similar in shape to the curve in FIG. 2 that results from the cumulative effects of the current through one or more junctions.
A second characteristic is a dependence of the current on temperature. Equation 1 explicitly includes temperature in the denominator of the exponential term. This would seem to imply that an increasing temperature causes a decrease in current for the diode (and thus any semiconductor junction with diode characteristics). The reality is normally the exact opposite because the reverse saturation component Io is also temperature dependent. The closer the applied voltage is to the forward conducting knee of the diode curve, the greater effect temperature will have on the current.
Capacitive lead-frame testing techniques rely on the ability of the tester to distinguish between very small differences in measured capacitance or measured current flow to allow the device tester to distinguish between the presence or non-presence of open, shorted, or otherwise defective joints of components of a device under test. Non-contact capacitive sensing testing techniques are described in detail in U.S. Pat. No. 5,557,209 to Crook et al, U.S. Pat. No. 5,498,964 to Kerschner et al., U.S. Pat. No. 5,420,500 to Kerschner, U.S. Pat. No. 5,254,953 to Crook et al., and U.S. Pat. No. 5,124,660 to Cilingiroglu, all of which are hereby incorporated by reference for all that they teach. In the past, as described previously, the geometry of the junctions were such that the traditional semiconductor junctions were characterized by a single threshold voltage—that is, all semiconductor junctions on a given device under test could be relied upon to turn on at or within a margin of error of a single threshold voltage (typically at approximately 700 mV). During a non-contact capacitive sensing test, therefore, this allowed the use of a single universal stimulus voltage level for stimulating all nodes under test of the device. The typical AC test stimulus voltage for capacitive lead-frame technologies has been set around 200 mV, at which it could be assumed that the junction current is sufficiently low to eliminate risk of damage to the device under test.
However, because advancements in semiconductor processing technology (shrinking geometries, changes in doping materials and doping concentrations, etc.) has lead to semiconductor junctions that turn on not at a single threshold voltage (or sharp knee), but rather semiconductor junctions that may be characterized by different junction characteristics relative to one another, and that turn on over a significant range of the stimulus voltage, the use of a single universal value of the stimulus voltage applied to all nodes under test of a device during a capacitive lead-frame test may be inappropriate, inefficient, or even problematic.
A technique has been developed as described in U.S. Patent Ser. No. 11/170,366 (publication number US2007/001687) in which semiconductor junction characteristics are utilized to find open connections at junctions between device under test nodes and nodes of components on the device under test.
Open connections are only one of several different types of manufacturing defects. Typical defect mechanisms can produce resistive joints with an elevated DC impedance. Resistive connections will have an unacceptably elevated series resistance between board-level signals and the intended IC pin connections. A “good” connection may have a series resistance in the milli-ohm range. Defective joints, such as those that are cracked by board flexure or those improperly wetted during solder reflow, may have series impedances much higher than normal, perhaps into the tens, to hundreds or even thousands of ohms. Such impedances might be tolerable on high-impedance inputs to ICs that do not draw a significant current during operation, but these impedances cannot be tolerated anywhere that significant currents do flow between IC and board-level signals. Their inserted impedance will cause unacceptable voltage drops that compromise circuit behavior.
Whereas open connections caused by missing solder may be evident using visual or X-Ray inspection, a resistive joint is quite often invisible to inspection. Therefore, a practical means of testing for resistance joints between IC pins and board-level signals is needed. This has become more prominent now that the electronics industry has moved towards new soldering technologies using lead-free alloys that are more prone to cracking and wetting problems.